The ptf 1210A LVDS Distribution uses high performance FPGA technology to precisely match the path times from the input pulse to all of the FPGA output LVDS signals. The propagation delay of electronic signals through normal copper wiring is approximately 1 nano second per foot. Through careful design in matching physical path lengths from the FPGA LVDS outputs,
the individual paths to all of the ptf 1210A outputs are matched in length, to insure the leading edge pulse synchronization is maintained.
In addition, the transmission line characteristics of the printed circuit board have been carefully designed to provide impedance matching, and preserve the integrity of the digital edges of the LVDS outputs. The individual expansion modules are connected to the FPGA base board by means of internal RJ45 connections and high performance, shielded twisted pair, cables.
In order to maintain the stringent performance of the unit, cable lengths have been carefully calculated to insure equal delays to all output connections, maintaining <2ns differential error between outputs.
The input to the LVDS Distribution unit is a CMOS level (5V nominal) pulse in the frequency range 0.5 Hz to 10 MHz.
This input pulse is converted internally within the ptf 1210A LVDS Distribution, to provide pseudo current loop LVDS outputs, at the same frequency as the input signal. Up to 60 parallel LVDS outputs can be accommodated by the unit, by fitting up to 15, 4 channel LVDS Distribution modules. The standard configuration is supplied with one expansion module (4 LVDS outputs) fitted.
Through high performance semiconductor technology, the ptf 1210A LVDS Distribution Unit maintains the leading edge of all pulse outputs to within 2ns of all other outputs.
• CMOS to LVDS Pulse Conversion
• Precision Matching of All Ouputs to Within <2ns
• Modular, Expandable Up to 60 Outputs
• Fault Alarm for Input Pulse Failure
• Convenient RJ12 Output Connections
• Accomodates Pulse Rates From 0.1 Hz to 10 MHz